1. Field of the Invention
This invention relates to sense amplifier circuits and, more particularly, to sense amplifier circuits that detect a potential difference between two nodes.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Sense amplifiers are commonly used in memory devices, such as random access memories (RAMs), read only memories (ROMs), and more specialized memories, such as content addressable memories (CAMs).
Continuing goals for nearly all integrated circuits include lower power consumption, higher operating speeds, and lower operating voltages. In the particular case of CAM devices, sensing operations can consume a considerable amount of current (and hence power), as such operations typically involve the continuous charging of multiple match lines, and the subsequent discharging of select match lines. Sense amplifier circuits are usually connected to such match lines to detect a match line state following a compare operation. For some conventional CAMs, a match line representing a match result (i.e., a HIT) will remain charged, while a match line representing a mismatch result (i.e., a MISS) is discharged to (or at least toward) a relatively low voltage power supply (e.g., Vss).
One conventional sense amplifier circuit is disclosed in “A Ternary Addressable Memory (TCAM) Based on 4T Static Storage and Including Current-Race Sensing Scheme,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, January 2003, pp. 155-158 by Arsovski et al. Another conventional sense amplifier circuit is shown in “A Current-Saving Match-Line Sensing Scheme for Content-Addressable Memories,” ISSCC 2003, Session 17, SRAM and DRAM, Paper 17.3 by Arsovski et al, pp. 304-305.
Yet another conventional sense amplifier is shown in FIG. 10. FIG. 10 shows an example of a single-ended sense amplifier employed in a ternary CAM device. In FIG. 10, sense amplifier 1000 is coupled to a compare stack 1002. Compare stack 1002 represents one of many bit compares in a sense operation. For example, bit compares may compare a compare data value (represented by complementary values CD and BCD) to a data value (represented by complementary values D and BD). In some cases, a compare result is maskable by a mask value MASK. Such masking capability is used to form a Mask-Value “ternary” CAM device, as opposed to a binary CAM device.
As shown in FIG. 10, conventional sense amplifier 1000 includes p-channel precharge transistors P1 and P2 having sources commonly connected to a power supply voltage (e.g., VCC), and gates commonly connected to a precharge signal (PRECHG). The conventional sense amplifier 1000 also includes a holding n-channel transistor N1 and sensing n-channel transistor N2. Transistors N1 and N2 may have drains connected to the drains of transistors P1 and P2, respectively. The sources of transistors N1 and N2 can be commonly connected to a match line 1004. The gates of transistors N1 and N2 can be commonly connected to another voltage (VCCQ). The VCCQ voltage may be included to maintain transistors N1 and N2 in an “off” state when match line 1004 is precharged to a high voltage potential, as will be described below.
The drain-drain connection of transistors P2 and N2 are connected to sense node 1006. Sense node 1006 can be precharged to a high precharge voltage (e.g., VCC) by precharge p-channel transistors P2. The potential at sense node 1006 can be buffered by series connected inverters INV1 and INV2 to provide the sense amplifier output signal (SAOUT). If p-channel P4 gate is connected to the bmsa node, the P4 gate can be (optionally) turned off by connecting it to the supply voltage (e.g. Vcc). P-channel transistors P3 and P4 are arranged in series forming a weak ½ latch between sense node 1006 and supply voltage VCC.
The operation of sense amplifier 1000 will now be described. In a pre-sense period, match line 1004 can be precharged to VCC-Vtn1, where Vtn1 is the threshold voltage of holding transistor N1. It is noted that sensing transistor N2 is designed to have a higher threshold voltage (e.g., at least 200 mV) than holding transistor N1. Thus, once match line 1004 is precharged to VCC-Vtn1, sensing transistor N2 is turned off.
In a sense period, data values (e.g., D and BD) can be compared to compare data (e.g., CD and BCD) within compare stack 1002. If the sense operation indicates a match (e.g., a HIT), all compare stacks (e.g., multiple compare stacks connected to match line 1004) will maintain a relatively high impedance between the match line 1004 and ground (VSS). In this state, sense amplifier 1000 utilizes the difference in threshold voltages of transistors N1 and N2 to keep transistor N2 in the “off” state. With transistor N2 turned off, sense node 1006 can be maintained at the relatively high precharged potential (e.g., VCC). In enabled, the weak ½ latch formed by p-channel devices P3 and P4 will also help to maintain sense node 1006 at its high voltage potential. This enables the sense amplifier output signal (SAOUT) to remain high, indicating a HIT state.
If the sense operation indicates a mis-match (e.g., a MISS), at least one compare stack will provide a relatively low impedance path between the match line 1004 and ground (VSS), causing match line 1004 to be discharged toward ground. When the gate to-source voltage of transistor N2 becomes larger than Vtn2, the sense transistor N2 will turn on. With transistor N2 on, sense node 1006 will discharge through sense transistor N2 and the compare stack 1002 to ground (VSS). This enables the sense amplifier output signal (SAOUT) to transition low, indicating a MISS state.
Thus, sense amplifier 1000 generally operates by precharging match line 1004 to VCC-Vtn1, and then discharging the same match line in the event of a MISS state. It is understood that a conventional CAM includes numerous match lines, and in a given sense operation, MISS states are far more common than HIT states. As a result, match operations in conventional sense amplifier circuits tend to consume considerable amounts of current, as match lines are continuously precharged and discharged
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.